1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and in particular to a nonvolatile semiconductor memory device in which a memory cell is formed of a stacked gate field effect transistor having a floating gate for accumulating electric charge to store data. More specifically, the present invention relates to a configuration for improving read margin in an AG (assist gate)-AND type flash memory utilizing an inversion layer formed on the surface of a substrate region as a bit line.
2. Description of the Background Art
In a nonvolatile semiconductor memory device, a memory cell transistor has a threshold voltage changed according to stored data. To read the data, a voltage of a certain level is applied to a control gate of the memory cell transistor and the amount of a current flowing through the memory cell transistor is sensed with a sense amplifier. During the data read, the drain side of the memory cell transistor is supplied with predetermined current and voltage, and the source side is grounded via a source line. The grounding is effected by connecting the source line to a common source line (common line) provided on one side of a memory array. Interconnection resistance is present in the source line, and source line resistance exists between a ground node and the memory cell transistor, of which value depends on the distance therebetween.
When a current flows through the source line, a voltage drop occurs according to the source line resistance, increasing a source potential of the memory cell transistor. If a constant voltage is applied to the control gate when the source potential is increased, a voltage Vgs between the control gate and the source is reduced, and an absolute value of the threshold voltage is increased due to a substrate effect (back gate effect). Accordingly, even in the case where the memory cell transistor is to be conductive when selected, it may not become so fully conductive as to drive a read current of a sufficient magnitude, which may cause a read error.
In particular, when the source line is formed of a diffusion layer or an inversion layer, its resistance value is increased, as compared to the case where it is formed of a metal interconnection line, and it also has great temperature dependency, so that the influence of variation of source line resistance of a memory cell transistor according to the position of the memory cell in an array is increased. In particular, when the source line is formed of an inversion layer, it resistance value is further increased compared to the case where it is formed of a diffusion layer, and thus the influence of variation becomes further greater.
Prior art Document 1 (Japanese Patent Laying-Open No. 2000-285692) discloses a configuration for reducing such dependency of the source line resistance on the position in an array. In the configuration described in Prior art Document 1, a voltage level applied to a word line (control gate) is changed according to a distance from a source line grounding node. A word line voltage is increased to compensate for an increase in source potential, and thus each memory cell has the same control gate to source voltage Vgs.
In Prior art Document 1, the voltage level for selecting a word line is changed according to the magnitude of the source line resistance, that is, the position of a memory cell. Accordingly, the voltage applied to a word line should be changed according to a selected row, complicating the control when selecting a word line.